`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/12/05 10:11:43
// Design Name: 
// Module Name: divider_1khz_1hz
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module divider_1khz_1hz(
    input clk_i,
    output reg clk_o
    );
    reg [9:0] timestamp = 'b0;
    always @(posedge clk_i) begin
        timestamp <= (timestamp==250) ? 1 : timestamp+1;
        if (timestamp<125) begin
            clk_o <= 1'b0;
        end else begin
            clk_o <= 1'b1;
        end
    end
endmodule
